AD1937 datasheet(19/36 Pages) AD

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AD1937

Rev. 0 | Page 19 of 36

SERIAL DATA PORTS—DATA FORMAT

The eight DAC channels use a common serial bit clock (DBCLK)

and a common left-right framing clock (DLRCLK) in the serial

data port. The four ADC channels use a common serial bit

clock (ABCLK) and left-right framing clock (ALRCLK) in the

serial data port. The clock signals are all synchronous with the

sample rate. The normal stereo serial modes are shown in

Figure 15.

The ADC and DAC serial data modes default to I2S stereo.

The ports can also be programmed for left-justified stereo,

right-justified stereo, and TDM modes. The word width is

24 bits by default and can be set to 16 or 20 bits in the DAC

Control 2 and ADC Control 1 registers. The DAC serial formats

are programmable in the DAC Control 0 register. The polarity of

DBCLK and DLRCLK is programmable in the DAC Control 1 reg-

ister. The ADC serial format is programmable in ADC Control 1

grammed in ADC Control 2 register. In Figure 2, Figure 3, and

Figure 15 all of the clocks are shown with their normal polarity.

Both DAC and ADC serial ports can be programmed to become

the bus masters according to DAC Control 1 and ADC Control 2

registers. By default, both ADC and DAC serial ports are in the

slave mode.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LSB

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL

DSP MODE—16 BITS TO 24 BITS PER CHANNEL

I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL

LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL

LRCLK

BCLK

SDATA

LSB

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT

fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.

3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.

MSB

Figure 15. Stereo Modes

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