TDA9210

12/19

Register Sub-addressed - I

For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed.

For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06).

For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).

Sub-address

Register Names

POR Value

Max.

Value

Hex

Dec

Hex

Dec

Hex

Dec

01

01

Contrast (CRT)

8-bit DAC

B4

180

FE

254

02

02

Brightness (BRT)

8-bit DAC

B4

180

FF

255

03

03

Drive 1 (DRV)

8-bit DAC

B4

180

FE

254

04

04

Drive 2 (DRV)

8-bit DAC

B4

180

FE

254

05

05

Drive 3 (DRV)

8-bit DAC

B4

180

FE

254

06

06

Not Used

-

-

-

-

07

07

OSD Contrast (OSD)

4-bit DAC

09

09

0F

15

08

08

BPCP & OCL

04

04

09

09

Miscellaneous

1C

28

0A

10

Cut Off Out 1 DC Level (Cut-off)

8-bit DAC

B4

180

FF

255

0B

11

Cut Off Out 2 DC Level (Cut-off)

8-bit DAC

B4

180

FF

255

0C

12

Cut Off Out 3 DC Level (Cut-off)

8-bit DAC

B4

180

FF

255

0D

13

Bandwidth Adjustment (BW)

4-bit DAC

07

07

0F

15

b7

b6

b5

b4

b3

b2

b1

b0

Function

POR Value

0

0

Internal BPCP triggered by HSYNC

x

0

1

Internal BPCP triggered by BLK

0

0

Internal BPCP synchronized by the trailing edge

x

0

1

Internal BPCP synchronized by the leading edge

0

0

0

Internal BPCP Width = 0.33

µs

0

0

1

Internal BPCP Width = 0.66

µsx

0

1

0

Internal BPCP Width = 1

µs

0

1

1

Internal BPCP Width = 1.33

µs

1

Internal BPCP = BPCP input (Pin 23)

0

Normal Operation

x

1

Reserved (Force BPCP to 1 in test)

0

Normal Operation

x

1

Reserved (Force OCL to 1 in test)

0

Internal OCL pulse triggered by BLK (pin 24)

x

1

Internal OCL pulse = Internal BPCP