TDA9109 datasheet(19/30 Pages) STMICROELECTRONICS

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OPERATING DESCRIPTION (continued)

H Osc

Sawtooth

H Drive

1.6V

4.0V

6.4V

7/8T

1/8T

Duty Cycle

Internally

Shaped Flyback

Flyback

The duty cycle of H-drive is adjustable between 30% and 60%.

Figure 11 : PLL2 Timing Diagram

H Osc

Sawtooth

Phase REF1

H Synchro

1.6V

6.4V

2.8V < Vb < 4.0V

7/8T

1/8T

Phase REF1 is obtained by comparison between the sawtooth and

a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-

sures the exact coincidence between the signal phase REF and

HSYNC. A

± TH/10 phase adjustment is possible.

Figure 10 : PLL1 Timing Diagram

The sync frequency must always be higher than the

free running frequency. For example, when using a

sync range between 24kHz and 100kHz, the sug-

gested free running frequency is 23kHz.

Another feature is the capability for the MCU to

force the horizontal frequency through I

2C to 2xf0

or 3xf0 (for burn-in mode or safety requirements).

In this case, the inhibition switch is opened, leaving

PLL1 free, but the voltage on PLL1 filter is forced

to 2.66V (for 2xf0) or 4.0V (for 3xf0).

PLL1 ensures the coincidence between the leading

edge of the sync signal and a phase reference

obtained by comparison between the sawtooth of

the VCO and an internal DC voltage which is I

adjustable between 2.8V and 4.0V (corresponding

± 10%) (see Figure 10).

The TDA9109/S also includes a Lock/Unlock iden-

tification block which senses in real time whether

PLL1 is locked or not on the incoming horizontal

sync signal. The resulting information is available

on HLOCKOUT (see Sync Processor).

When PLL1 is unlocked, it forces HLOCKOUT to

high level.

The lock/unlock information is also available

through the I

2C read.

II.3 - PLL2

PLL2 ensures a constant position of the shaped

flyback signal in comparison with the sawtooth of

the VCO, taking into account the saturation time Ts

(see Figure 11).

The phase comparator of PLL2 (phase type com-

parator) is followed by a charge pump (typical

output current : 0.5mA).

The flyback input consists of an NPN transistor.

This input must be current driven. The maxi-

mum r ec om mended input current is 5mA

(see Figure 12).

The duty cycle is adjustable through I

2C from 30%

to 60%. For start-up safe operation, the initial duty

cycle (after power-on reset) is 60% in order to avoid

having a too long conduction period of the horizon-

tal scanning transistor.

The maximum storage time (Ts Max.) is (0.44TH -

TFLY/2). Typically, TFLY/TH is around 20% which

means that Ts max is around 34% of TH.

TDA9109/S

19/30

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