M38045FFHKP datasheet(284/387 Pages) RENESAS

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APPLICATION

2.13 Flash memory mode

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

2.13.6 CPU rewrite mode

In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can

rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten

with the microcomputer itself mounted on board, without using the programmer.

Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot

be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to RAM,

execute it on the RAM.

The following commands can be used in the CPU rewrite mode: read array, read status register, clear

status register, program, and block erase. For details concerning each command, refer to “CHAPTER 1

Flash memory mode (CPU rewrite mode)”.

(1)

CPU rewrite mode beginning/release procedures

Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.

[Beginning procedure]

➀ Apply “H” to the CNVSS pin and P45/TxD1 pin (at selecting boot ROM area).

➁ Release reset.

➂ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register. (Make sure

that system clock

φ is less than 4.0 MHz.)

➃ After CPU rewrite mode control program is transferred to internal RAM, jump to this control

program on RAM. (The following operations are controlled by this control program).

➄ Set “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE16).

For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession.

➅ Set “1” to the all user block E/W enable bit (bit 4 of address 0FE216). Set the 8 KB user block

E/W enable bit. (Set to “0” when E/W is disabled, and set to “1” when E/W is enabled.)✽

✽ For these bits to be set to “1”, the user needs to write “0” and then “1” to those in succession.

➆ Flash memory operations are executed by using software commands.

Note 1: The following procedures are also necessary.

• Control for data which is input from the external (serial I/O etc.) and to be programmed

to the flash memory.

• Initial setting for ports, etc.

• Writing to the watchdog timer

[Release procedure]

➀ Execute the read array command.

➁ In order to disable E/W to the user ROM area (except for data block), set “0” to the all user block E/

W enable bit (bit 4 of 0FE216) and the 8 KB user block E/W enable bit (bit 2 of 0FE016) (Note 2).

➂ Set the CPU rewrite mode select bit (bit 1 of address 0FFE16) to “0”.

➃ Jump from the CPU rewriting control program on RAM to the user program on the flash memory.

Note 2: Although E/W inhibition is not indispensable, the safety of system improves by disabling

E/W except the time of E/W execution.

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