M38045FFHKP datasheet(281/387 Pages) RENESAS

281 / 387 page

2-157

APPLICATION

2.13 Flash memory mode

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.13.3 Structure of Flash memory control register 0

Fig. 2.13.2 Memory map of registers relevant to flash memory

2.13.3 Relevant registers

Flash memory control register 0 (FMCR0)

0FE016

Address

0FE116

0FE216

Flash memory control register 1 (FMCR1)

Flash memory control register 2 (FMCR2)

8 KB user block E/W

enable bit (Notes 1,

Flash memory control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Flash memory control register 0

(FMCR0 : address 0FE016)

Name

Functions

At reset R W

Not used (Do not write “1” to this bit.)

CPU rewrite mode

select bit (Note 1)

0 : Busy (being automatic written

or automatic erased)

1 : Ready

RY/BY status flag

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a

“1” to it in succession. For this bit to be set to “0”, write “0” only to

this bit.

2: This bit can be written only when the CPU rewrite mode select bit

is “1”.

3: Effective only when the CPU rewrite mode select bit = “1”. Fix this

bit to “0” when the CPU rewrite mode select bit is “0”.

4: When setting this bit to “1” (when the control circuit of flash memory

is reset), the flash memory cannot be accessed for 10

µs.

5: Write to this bit from program on RAM.

0: User ROM area is accessed

1: Boot ROM area is accessed

Flash memory reset

bit (Notes 3, 4)

0: Normal operation

1: Reset

0: E/W disabled

1: E/W enabled

0 : CPU rewrite mode invalid

(software commandes invalid)

1 : CPU rewrite mode valid

(Software commands

acceptable)

User ROM area

select bit (Note 5)

0: Pass

1: Error

Program status flag

0: Pass

1: Error

Erase status flag

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