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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38044FFHKP датащи(PDF) 272 Page - Renesas Technology Corp |
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M38044FFHKP датащи(HTML) 272 Page - Renesas Technology Corp |
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272 / 387 page  2-148 APPLICATION 2.11 Clock generating circuit Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.11.5 Control procedure Control procedure: To prepare for a power failure, set the relevant registers in the order shown below. Initialization CPUM (address 003B16), bit7, bit 6 CPUM (address 003B16), bit 4 0, 0 1 CPUM (address 003B16), bit7, bit 6 CPUM (address 003B16), bit5 1, 0 (Note) 1 (Note) RESET Internal system clock: f(XCIN)/2 (low-speed mode) Main clock f(XIN) oscillation stopped Note: Do not switch simultaneously. Return processing from power failure Set timer interrupt to occurs every second. Execute WIT instruction. At power failure, clock count is performed during timer interrupt processing (every second). Port XC: XCIN-XCOUT oscillation function When selecting main clock f(XIN)/2 (high-speed mode) Detect power failure ? N Y Return condition from power failure completed ? N Y qX: This bit is not used here. Set it to “0” or “1” arbitrarily. |
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