M38041FFHKP datasheet(349/387 Pages) RENESAS

349 / 387 page

3-59

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.5 Control registers

Fig. 3.5.13 Structure of Transmit/Receive buffer register 1, Transmit/Receive buffer register 3

Transmit/Receive buffer register 1, Transmit/Receive buffer register 3

b7 b6 b5 b4 b3 b2 b1 b0

Transmit/Receive buffer register 1 (TB1/RB1: address 001816)

Transmit/Receive buffer register 3 (TB3/RB3: address 003016)

Undefined

At reset R W

Functions

The transmission data is written to or the

receive data is read out from this buffer register.

• At write: A data is written to the transmit buffer

• At read: The contents of the receive buffer

Note: The contents of transmit buffer register cannot be read out.

The data cannot be written to the receive buffer register.

Undefined

Fig. 3.5.14 Structure of Serial I/O1 status register, Serial I/O3 status register

Serial I/O1 status register, Serial I/O3 status register

b7 b6 b5 b4 b3 b2 b1 b0

Serial I/O1 status register (SIO1STS: address 001916)

Serial I/O3 status register (SIO3STS: address 003116)

Name

Functions

At reset R W

Transmit buffer

empty flag (TBE)

Receive buffer full

flag (RBF)

0: Transmit shift in progress

1: Transmit shift completed

Transmit shift

completion flag

(TSC)

0: No error

1: Parity error

Parity error flag

(PE)

0: No error

1: Overrun error

Overrun error flag

(OE)

0: No error

1: Framing error

0: (OE) U (PE) U (FE) = 0

1: (OE) U (PE) U (FE) = 1

Framing error flag

(FE)

Summing error flag

(SE)

Nothing is arranged for this bit. This bit is a

write disabled bit. When this bit is read out, the

contents are “1”.

0: Buffer full

1: Buffer empty

0: Buffer empty

1: Buffer full

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