TMP102 datasheet(12/19 Pages) TI

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TIMING DIAGRAMS

TMP102

SBOS397B – AUGUST 2007 – REVISED OCTOBER 2008 ............................................................................................................................................... www.ti.com

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

The TMP102 is two-wire and SMBus compatible.

limited and is determined by the master device. It is

Figure

describe

the

various

also possible to use the TMP102 for single byte

operations on the TMP102. Parameters for Figure 12

updates. To update only the MS byte, terminate the

are defined in Table 13. Bus definitions are:

communication

issuing

START

STOP

communication on the bus.

Bus Idle: Both SDA and SCL lines remain high.

Acknowledge:

Each

receiving

device,

when

Start Data Transfer: A change in the state of the

addressed, is obliged to generate an Acknowledge

SDA line, from high to low, while the SCL line is high,

bit. A device that acknowledges must pull down the

defines a START condition. Each data transfer is

SDA line during the Acknowledge clock pulse in such

initiated with a START condition.

a way that the SDA line is stable low during the high

Stop Data Transfer: A change in the state of the

period of the Acknowledge clock pulse. Setup and

SDA line from low to high while the SCL line is high

hold times must be taken into account. On a master

defines a STOP condition. Each data transfer is

receive, the termination of the data transfer can be

terminated

with

repeated

START

STOP

signaled

the

master

generating

condition.

Not-Acknowledge ('1') on the last byte that has been

transmitted by the slave.

Table 13. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

f(SCL)

SCL Operating Frequency, VS > 1.7V

0.001

0.4

0.001

3.4

MHz

f(SCL)

SCL Operating Frequency, VS < 1.7V

0.001

0.4

0.001

2.75

MHz

Bus Free Time Between STOP and START

t(BUF)

600

160

Condition

Hold time after repeated START condition.

t(HDSTA)

100

After this period, the first clock is generated.

t(SUSTA)

Repeated START Condition Setup Time

100

t(SUSTO)

STOP Condition Setup Time

100

t(HDDAT)

Data Hold Time

t(SUDAT)

Data Setup Time

100

t(LOW)

SCL Clock Low Period, VS > 1.7V

1300

160

t(LOW)

SCL Clock Low Period, VS < 1.7V

1300

200

t(HIGH)

SCL Clock High Period

600

Clock/Data Fall Time

300

Clock/Data Rise Time

300

160

Clock/Data Rise Time for SCLK

≤ 100kHz

1000

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