TAS3218IPZPR datasheet(40/79 Pages) TI

40 / 79 page

54-BIT INSTRUCTION

TAS3208 instruction word

Contains two dummy bits in every instruction word of the EEPROM.

All TAS3208 tool compilers always ZERO to these dummy bits in the compile EEPROM image.

DUM

ALU First Stage

ALU Second Stage

Data Memory Load

Coefficient Memory Load

Memory Store

P1OP

P2OP

MOP1

AD1

MOP2

AD2

MOP3

AD3

54–55

53–49

48–42

41–37

36–27

23–14

26–24

9–0

13–10

54-BIT INSTRUCTION

New “Ext”-ended field

Extension bit designates offset of 1K to these

address references for LD/ST operations

Ext

ALU First Stage

ALU Second Stage

Data Memory Load

Coefficient Memory Load

Memory Store

P1OP

P2OP

MOP1

AD1

MOP2

AD2

MOP3

AD3

53–49

48–42

41–37

36–27

23–14

26–24

9–0

13–10

DSP Instruction Set

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

The superset instruction word maintains backward compatibility with the 54-bit instruction word of the TAS3218

device, since the 54 bit instruction word required dummy storage of 2 bits in the EEPROM.

Figure 31. Instruction Word

As shown in Figure 32 the extension bit designates an offset of 1K to all three addresses in the instruction word.

However, it should be noted that both data and coefficient memory addresses above the 1K boundary are

reserved for housekeeping processing tasks. Any attempt to write to these addresses may corrupt the audio

output.

Figure 32. Instruction Word Extension Field

Please see the TAS3xxx Programmers Guide for detailed information regarding programming of this device.

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