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7480 датащи(PDF) 13 Page - Renesas Technology Corp

номер детали 7480
подробное описание детали  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
PDF  337 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7480 датащи(HTML) 13 Page - Renesas Technology Corp

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List of Figures
iii
7480 Group and 7481 Group User’s Manual
Figure 1.14.1 Memory Map of Registers Associated with Serial I/O.................................. 1-107
Figure 1.14.2 Transmit/Receive Buffer Register .................................................................... 1-108
Figure 1.14.3 Serial I/O Status Register ................................................................................ 1-109
Figure 1.14.4 Serial I/O Control Register ............................................................................... 1-111
Figure 1.14.5 UART Control Register ..................................................................................... 1-112
Figure 1.14.6 Baud Rate Generator ........................................................................................ 1-113
Figure 1.14.7 Bus Collision Detection Control Register ....................................................... 1-113
Figure 1.14.8 Block Diagram of Clock Synchronous Serial I/O .......................................... 1-116
Figure 1.14.9 Transmit Operation of Clock Synchronous Serial I/O .................................. 1-118
Figure 1.14.10 Transmit Timing of Clock Synchronous Serial I/O ...................................... 1-118
Figure 1.14.11 Receive Operation of Clock Synchronous Serial I/O ................................. 1-120
Figure 1.14.12 Receive Timing of Clock Synchronous Serial I/O ....................................... 1-120
Figure 1.14.13 Setting of Clock Synchronous Serial I/O (1) ............................................... 1-121
Figure 1.14.14 Setting of Clock Synchronous Serial I/O (2) ............................................... 1-122
Figure 1.14.15 Data Transfer Formats in UART ................................................................... 1-128
Figure 1.14.16 Block Diagram of UART ................................................................................. 1-129
Figure 1.14.17 Transmit Operation of UART ......................................................................... 1-131
Figure 1.14.18 Transmit Timing example in UART ............................................................... 1-131
Figure 1.14.19 Receive Operation of UART .......................................................................... 1-133
Figure 1.14.20 Receive Timing Example in UART ............................................................... 1-133
Figure 1.14.21 Setting of UART (1) ........................................................................................ 1-134
Figure 1.14.22 Setting of UART (2) ........................................................................................ 1-135
Figure 1.14.23 Contention bus system communications ...................................................... 1-138
Figure 1.14.24 Block Diagram of Bus Arbitration Interrupt .................................................. 1-138
Figure 1.14.25 Timing of Bus Collision Detection ................................................................. 1-139
Figure 1.14.26 Setting of Bus Arbitration Interrupt ............................................................... 1-140
Figure 1.15.1 Block Diagram of A-D Converter..................................................................... 1-141
Figure 1.15.2 Memory Map of Registers Associated with A-D Converter ......................... 1-142
Figure 1.15.3 A-D Control Register ......................................................................................... 1-142
Figure 1.15.4 A-D Conversion Register .................................................................................. 1-143
Figure 1.15.5 Change of A-D Conversion Register and Comparison Voltage during A-D Conversion ..... 1-145
Figure 1.15.6 Setting of A-D Conversion ............................................................................... 1-146
Figure 1.15.7 Internal equivalent circuit of analog input circuit .......................................... 1-148
Figure 1.16.1 Block Diagram of Watchdog Timer ................................................................. 1-149
Figure 1.16.2 Memory Map of Registers Associated with Watchdog Timer ...................... 1-149
Figure 1.16.3 Watchdog Timer H ............................................................................................ 1-150
Figure 1.16.4 CPU Mode Register .......................................................................................... 1-150
Figure 1.16.5 Internal Processing Sequence during Reset by Watchdog Timer ............. 1-152
Figure 1.16.6 Setting of Watchdog Timer .............................................................................. 1-153
Figure 1.17.1 Internal Processing Sequence after Reset Release ..................................... 1-155
Figure 1.17.2 Internal State at Reset ..................................................................................... 1-156
Figure 1.18.1 Block Diagram of Clock Generator ................................................................. 1-158
Figure 1.18.2 Memory Map of Register Associated with Oscillation Circuit ...................... 1-159
Figure 1.18.3 CPU Mode Register .......................................................................................... 1-159
Figure 1.18.4 Oscillator Start-Up Stabilization Time at Power On ..................................... 1-161
Figure 1.19.1 Transitions from Power Saving Modes ........................................................... 1-163
Figure 1.19.2 Memory Map of Registers Associated with Power Saving .......................... 1-164
Figure 1.19.3 STP Instruction Operation Control Register .................................................. 1-164
Figure 1.19.4 Edge Polarity Selection Register ..................................................................... 1-165
Figure 1.19.5 Operation at Recovery from Stop Mode by Reset Input ............................. 1-166
Figure 1.19.6 Operation Example at Recovery from Stop Mode by INT0 Interrupt ......... 1-167
Figure 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions ................................... 1-169



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