38C3 datasheet(46/224 Pages) RENESAS

46 / 224 page

38C3 Group User’s Manual

HARDWARE

1-31

LCD DRIVE CONTROL CIRCUIT

The 38C3 group has the built-in Liquid Crystal Display (LCD) drive

control circuit consisting of the following.

•

LCD display RAM

•

Segment output enable register

•

LCD mode register

•

Selector

•

Timing controller

•

Common driver

•

Segment driver

•

Bias control circuit

A maximum of 32 segment output pins and 4 common output pins

can be used.

Up to 128 pixels can be controlled for a LCD display. When the LCD

enable bit is set to “1” after data is set in the LCD mode register, the

Fig. 29 Structure of LCD related registers

segment output enable register, and the LCD display RAM, the LCD

drive control circuit starts reading the display data automatically, per-

forms the bias control and the duty ratio control, and displays the

data on the LCD panel.

Table 10 Maximum number of display pixels at each duty ratio

Duty ratio

Maximum number of display pixels

32 dots

or 8 segment LCD 4 digits

64 dots

or 8 segment LCD 8 digits

96 dots

or 8 segment LCD 12 digits

128 dots

or 8 segment LCD 16 digits

FUNCTIONAL DESCRIPTION

Segment output enable bit 0

0 : I/O ports P20–P23

1 : Segment output SEG0–SEG3

Segment output enable bit 1

0 : I/O ports P24–P27

1 : Segment output SEG4–SEG7

Segment output enable bit 2

0 : I/O ports P00–P03

1 : Segment output SEG8–SEG11

Segment output enable bit 3

0 : I/O ports P04–P07

1 : Segment output SEG12–SEG15

Segment output enable bit 4

0 : I/O ports P10–P13

1 : Segment output SEG16–SEG19

Segment output enable bit 5

0 : I/O ports P14–P17

1 : Segment output SEG20–SEG23

Segment output enable bit 6

0 : Output ports P30–P33

1 : Segment output SEG24–SEG27

Segment output enable bit 7

0 : Output ports P34–P37

1 : Segment output SEG28–SEG31

Segment output enable register

(SEG : address 003816)

LCD mode register

(LM : address 003916)

Duty ratio selection bits

0 0 : 1 (use COM0)

0 1 : 2 (use COM0,COM1)

1 0 : 3 (use COM0–COM2)

1 1 : 4 (use COM0–COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

Not used (returns “0” when read)

(Do not write “1” to this bit.)

LCD circuit divider division ratio selection bits

0 0 : Clock input

0 1 : 2 division of clock input

1 0 : 4 division of clock input

1 1 : 8 division of clock input

LCDCK count source selection bit (Note)

0 : f(XCIN)/32

1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)

Note : LCDCK is a clock for a LCD timing controller.

38C3 датащи(PDF) 46 Page - Renesas Technology Corp

38C3 датащи(HTML) 46 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL