32172 datasheet(49/875 Pages) RENESAS

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2-4

Rev.1.0

CPU

2.3 Control Registers

2.3.1 Processor Status Word Register: PSW (CR0)

The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists

of a regularly used PSW field and a special BPSW field which is used to save the PSW field when

an EIT occurs.

The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and

Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit

(BSM), Backup IE bit (BIE), and Backup C bit (BC).

Bit Name

Function

Initial

BSM (Backup SM)

Holds the value of SM bit when EIT

Indeterminate

is accepted.

BIE (Backup IE)

Holds the value of IE bit when EIT

Indeterminate

is accepted.

BC (Backup C)

Holds the value of C bit when EIT

Indeterminate

is accepted.

SM (Stack Mode)

0: Interrupt stack pointer is used.

1: User stack pointer is used.

IE (Interrupt Enable)

0: No interrupt is accepted.

1: Interrupt is accepted.

C (Condition bit)

Depending on instruction execution, it indicates

whether operation resulted in a carry, borrow, or overflow.

Note 1: "Initial" shows the state immediately after reset, R = O means the register is readable,

W = O means the register is writable.

Note 2: For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT.”

(Note 1)

16 17

23 24 25

31(LSB)

0(MSB)

BSM

BIE

PSW

BPSW field

PSW field

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