SH7764 datasheet(39/1752 Pages) RENESAS

39 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xxxix of lvi

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Figure 20.1 Configuration of E-DMAC, and Descriptors and Buffers.......................................... 750

Figure 20.2 Relationship between Transmit Descriptor and Transmit Buffer............................... 787

Figure 20.3 Relationship between Receive Descriptor and Receive Buffer.................................. 791

Figure 20.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) ................................... 796

Figure 20.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor).................................. 798

Figure 20.6 E-DMAC Operation after Transmit Error .................................................................. 799

Figure 20.7 E-DMAC Operation after Receive Error.................................................................... 800

Section 21 USB 2.0 Host/Function Module (USB)

Figure 21.1 UBS Connector Connection ....................................................................................... 935

Figure 21.2 Items Relating to Interrupts........................................................................................ 940

Figure 21.3 Timing at which a BRDY Interrupt is Generated....................................................... 945

Figure 21.4 Timing at which NRDY Interrupt is Generated when Function Controller

Function is Selected ................................................................................................... 951

Figure 21.5 Timing at which BEMP Interrupt is Generated when Function Controller

Function is Selected ................................................................................................... 953

Figure 21.6 Device State Transitions............................................................................................. 954

Figure 21.7 Control Transfer Stage Transitions ............................................................................ 956

Figure 21.8 Example of SOFR Interrupt Output Timing............................................................... 957

Figure 21.9 Example of a Buffer Memory Map ............................................................................ 970

Figure 21.10 Example of Buffer Memory Settings ....................................................................... 974

Figure 21.11 Example of Buffer Memory Operation .................................................................... 976

Figure 21.12 Token Issuance when IITV = 0 ................................................................................ 990

Figure 21.13 Token Issuance when IITV = 1 ................................................................................ 991

Figure 21.14 Relationship between (

µ) Frames and Expected Token Reception when

IITV = 0 ................................................................................................................... 992

Figure 21.15 Relationship between (

µ) Frames and Expected Token Reception when

IITV

≠ 0 ...................................................................................................................993

Figure 21.16 Example of Data Setup Function Operation............................................................. 995

Figure 21.17 Example of Buffer Flush Function Operation .......................................................... 996

Figure 21.18 Example of an Interval Error Being Generated when IITV = 1 ............................... 997

Section 22 LCD Controller (LCDC)

Figure 22.1 LCDC Block Diagram.............................................................................................. 1002

Figure 22.2 Valid Display and the Retrace Period ...................................................................... 1038

Figure 22.3 Color-Palette Data Format ....................................................................................... 1039

Figure 22.4 Power-Supply Control Sequence and States of the LCD Module ............................ 1045

Figure 22.5 Power-Supply Control Sequence and States of the LCD Module ............................ 1045

Figure 22.6 Power-Supply Control Sequence and States of the LCD Module ............................ 1046

Figure 22.7 Power-Supply Control Sequence and States of the LCD Module ............................ 1046

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