M38049FFHKP datasheet(282/387 Pages) RENESAS

282 / 387 page

2-158

APPLICATION

2.13 Flash memory mode

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.13.4 Structure of Flash memory control register 1

Fig. 2.13.5 Structure of Flash memory control register 2

Flash memory control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Flash memory control register 1

(FMCR1 : address 0FE116)

Name

Functions

At reset R W

Nothing is arranged for these bits. If writing to

these bits, write “0”. The contents are undefined

at reading.

Erase suspend

request bit (Note 2)

0 : Suspend invalid

1 : Suspend valid

Erase suspend

enable bit (Note 1)

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then

a “1” to it in succession.

2: Only when the erase suspend bit is “1”, this bit is valid.

0 : Erase restart (no

request issued)

1 : Suspend request

(request issued)

Erase suspend flag

0 : Erase active

1 : Erase inactive (Erase

suspend mode)

Nothing is arranged for these bits. If writing to

these bits, write “0”. The contents are undefined

at reading.

Flash memory control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Flash memory control register 2

(FMCR2 : address 0FE216)

Name

Functions

At reset R W

Nothing is arranged for these bits. If writing to

these bits, write “0”. The contents are undefined

at reading.

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then

a “1” to it in succession.

2: Effective only when the CPU rewrite mode select bit = “1”.

All user block E/W

enable bit (Notes 1, 2)

0 : E/W disabled

1 : E/W enabled

Nothing is arranged for these bits. If writing to

these bits, write “0”. The contents are undefined

at reading.

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