M38049FFHKP datasheet(71/387 Pages) RENESAS

71 / 387 page

1-53

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

3. SRDY3 output of reception side

q Note

When signals are output from the SRDY3 pin on the reception side

by using an external clock in the clock synchronous serial I/O

mode, set all of the receive enable bit, the SRDY3 output enable

bit, and the transmit enable bit to “1” (transmit enabled).

4. Setting serial I/O3 control register again

q Note

Set the serial I/O3 control register again after the transmission and

the reception circuits are reset by clearing both the transmit en-

able bit and the receive enable bit to “0.”

5. Data transmission control with referring to transmit shift

q Note

After the transmit data is written to the transmit buffer register, the

transmit shift register completion flag changes from “1” to “0” with

a delay of 0.5 to 1.5 shift clocks. When data transmission is con-

trolled with referring to the flag after writing the data to the transmit

buffer register, note the delay.

6. Transmission control when external clock is selected

q Note

When an external clock is used as the synchronous clock for data

transmission, set the transmit enable bit to “1” at “H” of the SCLK3

input level. Also, write data to the transmit buffer register at “H” of

the SCLK input level.

7. Transmit interrupt request when transmit enable bit is set

q Note

When using the transmit interrupt, take the following sequence.

➀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled).

➁ Set the transmit enable bit to “1”.

➂ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or

more instruction has executed.

➃ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled).

q Reason

When the transmit enable bit is set to “1”, the transmit buffer

empty flag and the transmit shift register shift completion flag are

also set to “1”. Therefore, regardless of selecting which timing for

the generating of transmit interrupts, the interrupt request is gener-

ated and the transmit interrupt request bit is set at this point.

Clear both the transmit enable bit

(TE) and the receive enable bit

(RE) to “0”

↓

Set the bits 0 to 3 and bit 6 of the

serial I/O3 control register

↓

Set both the transmit enable bit

(TE) and the receive enable bit

(RE), or one of them to “1”

Can be set with the

LDM instruction at the

same time

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