M38049FFHKP datasheet(238/387 Pages) RENESAS

238 / 387 page

2-114

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2004

REJ09B0212-0100Z

3804 Group (Spec.H)

2.5.7 Notes on multi-master I2C-BUS interface

(1)

Read-modify-write instruction

Each register of the multi-master I2C-BUS interface has bits to change by hardware. The precautions

when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the

multi-master I2C-BUS interface are described below.

➀ I2C data shift register (S0: address 001116)

When executing the read-modify-write instruction for this register during transfer, data may become

a value not intended.

➁ I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916)

When the read-modify-write instruction is executed for this register at detecting the STOP condition,

data may become a value not intended.

q Reason

It is because hardware changes the read/write bit (RWB) at detecting the STOP condition.

➂ I2C status register (S1: address 001316)

Do not execute the read-modify-write instruction for this register because all bits of this register

are changed by hardware.

➃ I2C control register (S1D: address 001416)

When the read-modify-write instruction is executed for this register at detecting the START condition

or at completing the byte transfer, data may become a value not intended.

q Reason

Because hardware changes the bit counter (BC0 to BC2).

➄ I2C clock control register (S2: address 001516)

The read-modify-write instruction can be executed for this register.

➅ I2C START/STOP condition control register (S2D: address 001616)

The read-modify-write instruction can be executed for this register.

M38049FFHKP датащи(PDF) 238 Page - Renesas Technology Corp