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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38049FFHKP датащи(PDF) 229 Page - Renesas Technology Corp |
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M38049FFHKP датащи(HTML) 229 Page - Renesas Technology Corp |
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229 / 387 page  2-105 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) ➄ Transmission of upper data Confirm correct completion of communication at ➃ before receiving the upper data. After confirming correct completion, store the received data (lower data). Set the ACK bit (bit 6 of address 001516) to “1”, in which ACK is not returned and write dummy data to the I2C data shift register (address 001116). When the MST bit (bit 7 of address 001316) is “0”, return to the process ➀, because other devices have priority to communicate. Fig. 2.5.26 Reception process of upper data AL (address 001316), bit 3 ? MST (address 001316), bit 7 ? 1 (Master) Receive data buffer ← S0 (address 001116) 0 (slave) 1(detected) 0 (not detected) End Re-transmission preparation Error processing S2 (address 001516) ←110001012 S0 (address 001116) ← 111111112 PIN (address 001316), bit 4 ? 1 (STOP condition) 0 (lower data transmitted) 5 • Judgment of bus hold • Judgment of arbitration lost detection • “NACK is returned” set • Judgment of slave mode detection • Dummy data to I2C data shift register write • Receive data read and save |
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