M38049FFHKP datasheet(220/387 Pages) RENESAS

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2-96

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

(5)

ACK bit

The ACK bit clock is generated by the master. This is used for indication of acknowledgment on the

SDA line, the slave’s busy and the data end.

For example, the slave device makes the SDA line “L” for acknowledgment when confirming the slave

address following the START condition. The built-in I2C-BUS interface has the slave address automatic

judgment function and the ACK acknowledgment function. “L” is automatically output when the ACK

bit of I2C clock control register (bit 6 of address 001516) is “0” and an address data is received. When

the slave address and the address data do not correspond, “H” (NACK) is automatically output.

In case the slave device cannot receive owing to an interrupt process, performing operation or

others, the master can output STOP condition and complete data transfer by making the ACK data

of the slave address “H” for acknowledgment. Even in case the slave device cannot receive data

during data transferring, the communication can be interrupted by performing NACK acknowledgment

to the following data.

When the master is receiving the data from the slave, the master can notify the slave of completion

of data reception by performing NACK acknowledgment to the last data received from the slave.

(6)

RESTART condition

The master can receive or transmit data without transmission of STOP condition while the master is

transmitting or receiving a data.

For example, after the master transmitted a data to the slave, transmitting a slave address + R

(Read) following RESTART condition can make the following data treat as a reception data.

Additionally, transmitting a slave address + W (Write) following RESTART condition can make the

following data treat as a transmission data.

Fig. 2.5.18 RESTART condition of master reception

2.5.5 Synchronization and arbitration lost

(1)

Synchronization

When a plural master exists on the I2C-BUS and the masters, which have different speed, are going

to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be

output correctly.

Figure 2.5.19 shows a synchronized SCL line example. The SCL (A) and the SCL (B) are the master

devices having a different speed. The SCL is synchronized waveforms.

As shown by Figure 2.5.19, the SCL lines can be synchronized by the following method; the device

which first finishes “H” term makes the SCL line “L” and the device which last remains “L” makes the

SCL line “H”.

R/W

R/W A

Slave address

7 bits

“0”

8 bits7 bits8 bits8 bits

“1”

Slave address

Data

START conditionRESTART condition

Master reception

1st-byte

Master reception

2nd-byte

NACK expression end of

master reception data

Lower data

Upper data

Master to slave

Slave to master

S: START condition

A: ACK bit

Sr: RESTART condition

P: STOP condition

R/W: Read/Write bit

Write

Read

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