M38049FFHKP datasheet(209/387 Pages) RENESAS

209 / 387 page

2-85

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.5.2 Structure of MISRG

MISRG

b7 b6 b5 b4 b3 b2 b1 b0

MISRG

(MISRG: address 001016)

0: Automatically set (Note 1)

1: Autimatically set disabled

Oscillation stabilizing

time set after STP

instruction released bit

Middle-speed mode

automatic switch set

bit

Middle-speed mode

automatic switch

start bit

(Depending on

program)

Middle-speed mode

automatic switch

wait time set bit

Functions

Name

At reset R W

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are 0 .

0: Not set automatically

1: Automatic switching

enabled (Notes 2, 3)

0: 4.5 to 5.5 machine cycles

1: 6.5 to 7.5 machine cycles

0: Invalid

1: Automatic switch start

(Note 3)

Notes 1: 0116 is set to Timer 1, FF16 is set to Prescaler 12.

2: During operation in low-speed mode, it is possible automatically to switch to

middle-speed mode owing to the rising of SCL/SDA.

3: When automatic switch to middle-speed mode from low-speed mode occurs,

the values of CPU mode register (003B16) change.

Fig. 2.5.3 Structure of I2C data shift register

I2C data shift register

b7 b6 b5 b4 b3 b2 b1 b0

I2C data shift register

(S0: address 001116)

Undefined

At reset R W

Functions

• 8-bit shift register to store receive data and

write transmit data.

Note: When data is written to I2C data shift register after the MST

bit is set to “0” (slave mode), keep the interval for 8 machine

cycles or more.

Also, when the read-modify-write instructions (SEB, CLB) are

used during data transfer, the values may be undefined.

Undefined

2.5.2 Relevant registers

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