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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M38049FFHKP датащи(PDF) 196 Page - Renesas Technology Corp |
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M38049FFHKP датащи(HTML) 196 Page - Renesas Technology Corp |
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196 / 387 page  2-72 APPLICATION 2.4 Serial interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) The communication is performed according to the timing shown in Figure 2.4.34. In the slave unit, when a synchronous clock is not input within a certain time (heading adjustment time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.4.35 shows relevant registers setting. Fig. 2.4.34 Timing chart Fig. 2.4.35 Relevant registers setting D0 Byte cycle Block transfer term Block transfer cycle D1 D2 D7 D0 Interval between blocks Processing for heading adjustment Heading adjustment time Master unit Transmit enabled SIO1CON Serial I/O1 control register (Address : 001A16) Synchronous clock : BRG/4 Transmit interrupt source : Transmit shift operating completion Receive enabled Clock synchronous serial I/O 0 1 1 11 0 0 1 Serial I/O1 enabled BRG count source : f(XIN) SRDY1 output disabled Not be affected by external clock Transmit enabled SIO1CON Serial I/O1 control register (Address : 001A16) Not use the serial I/O1 transmit interrupt Receive enabled Clock synchronous serial I/O 1 1 1 1 Slave unit 1 Serial I/O1 enabled 0 Synchronous clock : External clock UART1CON UART1 control register (Address : 001B16) P45/TXD1 pin : CMOS output 0 Both of units b7 b0 8 – 1 BRG1 b7 b0 Baud rate generator 1 (Address : 001C16) Set “division ratio – 1” b7 b0 b7 b0 SRDY1 output disabled |
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