M38049FFHKP datasheet(330/387 Pages) RENESAS

330 / 387 page

3-40

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

APPENDIX

3.3 Notes on use

3.3.18 Notes on wait mode

sClock restoration

If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is

stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and

XIN is set as the system clock.

In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.

3.3.19 Notes on CPU rewrite mode

(1)

Operation speed

During CPU rewrite mode, set the system clock

φ 4.0 MHz or less using the main clock division ratio

selection bits (bits 6 and 7 of address 003B16).

(2)

Instructions inhibited against use

The instructions which refer to the internal data of the flash memory cannot be used during the CPU

rewrite mode.

(3)

Interrupts inhibited against use

The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data

of the flash memory.

(4)

Watchdog timer

In case of the watchdog timer has been running already, the internal reset generated by watchdog

timer underflow does not happen, because of watchdog timer is always clearing during program or

erase operation.

(5)

Reset

Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the

program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.

3.3.20 Notes on programming

(1)

Processor status register

➀ Initializing of processor status register

Flags which affect program execution must be initialized after a reset.

In particular, it is essential to initialize the T and D flags because they have an important effect

on calculations.

q Reason

After a reset, the contents of the processor status register (PS) are undefined except for the I

flag which is “1”.

Fig. 3.3.5 Initialization of processor status register

Reset

↓

Initializing of flags

↓

Main program

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