SH7641 datasheet(21/1036 Pages) RENESAS

21 / 1036 page

Rev. 4.00 Sep. 14, 2005 Page xxi of l

18.3.7 Timer General Register (TGR) ............................................................................. 553

18.3.8 Timer Start Register (TSTR) ................................................................................ 554

18.3.9 Timer Synchro Register (TSYR) .......................................................................... 554

18.3.10 Timer Output Master Enable Register (TOER) .................................................... 556

18.3.11 Timer Output Control Register (TOCR) ............................................................... 557

18.3.12 Timer Gate Control Register (TGCR) .................................................................. 559

18.3.13 Timer Subcounter (TCNTS) ................................................................................. 561

18.3.14 Timer Dead Time Data Register (TDDR)............................................................. 561

18.3.15 Timer Period Data Register (TCDR) .................................................................... 561

18.3.16 Timer Period Buffer Register (TCBR).................................................................. 561

18.3.17 Bus Master Interface ............................................................................................. 562

18.4

Operation ........................................................................................................................... 562

18.4.1 Basic Functions..................................................................................................... 562

18.4.2 Synchronous Operation......................................................................................... 568

18.4.3 Buffer Operation ................................................................................................... 571

18.4.4 Cascaded Operation .............................................................................................. 574

18.4.5 PWM Modes ......................................................................................................... 576

18.4.6 Phase Counting Mode ........................................................................................... 581

18.4.7 Reset-Synchronized PWM Mode.......................................................................... 588

18.4.8 Complementary PWM Mode................................................................................ 591

18.5

Interrupts............................................................................................................................ 616

18.5.1 Interrupts and Priority ........................................................................................... 616

18.5.2 DMA Activation ................................................................................................... 618

18.5.3 A/D Converter Activation..................................................................................... 618

18.6

Operation Timing............................................................................................................... 619

18.6.1 Input/Output Timing ............................................................................................. 619

18.6.2 Interrupt Signal Timing......................................................................................... 624

18.7

Usage Notes ....................................................................................................................... 627

18.7.1 Module Standby Mode Setting ............................................................................. 627

18.7.2 Input Clock Restrictions ....................................................................................... 627

18.7.3 Caution on Period Setting ..................................................................................... 628

18.7.4 Conflict between TCNT Write and Clear Operations .......................................... 628

18.7.5 Conflict between TCNT Write and Increment Operations ................................... 629

18.7.6 Conflict between TGR Write and Compare Match............................................... 630

18.7.7 Conflict between Buffer Register Write and Compare Match .............................. 630

18.7.8 Conflict between TGR Read and Input Capture ................................................... 632

18.7.9 Conflict between TGR Write and Input Capture .................................................. 633

18.7.10 Conflict between Buffer Register Write and Input Capture.................................. 634

18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection ........... 634

18.7.12 Counter Value during Complementary PWM Mode Stop .................................... 636

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