3822 datasheet(13/328 Pages) RENESAS

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List of figures

3822 GROUP USER’S MANUAL

CHAPTER 3. APPENDIX

Fig. 3.1.1 Pin configuration of EPROM version (top view) ................................................................ 3-4

Fig. 3.1.2 Pin configuration of One Time PROM version (top view) (1) ............................................. 3-5

Fig. 3.1.3 Pin configuration of One Time PROM version (top view) (2) ............................................. 3-6

Fig. 3.1.4 Functional block diagram of built-in PROM version ........................................................... 3-7

Fig. 3.1.5 Programming and testing of One Time PROM version (shipped in blank) ........................ 3-9

Fig. 3.2.1 Wiring for the RESET input pin ........................................................................................ 3-10

Fig. 3.2.2 Wiring for clock I/O pins ................................................................................................... 3-10

Fig. 3.2.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ........................ 3-11

Fig. 3.2.4 Bypass capacitor across the VSS line and the VCC line ................................................... 3-11

Fig. 3.2.5 Analog signal line and a resistor and a capacitor ............................................................ 3-12

Fig. 3.2.6 Wiring for large current signal line ................................................................................... 3-12

Fig. 3.2.7 Wiring to a signal line where potential levels change frequently ..................................... 3-13

Fig. 3.2.8 VSS pattern on the underside of an oscillator .................................................................. 3-13

Fig. 3.2.9 Setup for I/O ports ........................................................................................................... 3-13

Fig. 3.2.10 Watchdog timer by software .......................................................................................... 3-14

Fig. 3.3.1 Structure of port P0 and P1 direction registers ................................................................ 3-15

Fig. 3.3.2 Structure of port Pi (i = 2, 4 to 7) direction registers ........................................................ 3-15

Fig. 3.3.3 Structure of PULL register A ............................................................................................ 3-16

Fig. 3.3.4 Structure of PULL register B ............................................................................................ 3-16

Fig. 3.3.5 Structure of serial I/O status register ............................................................................... 3-17

Fig. 3.3.6 Structure of serial I/O control register .............................................................................. 3-18

Fig. 3.3.7 Structure of UART control register .................................................................................. 3-19

Fig. 3.3.8 Structure of timer X mode register ................................................................................... 3-20

Fig. 3.3.9 Structure of timer Y mode register ................................................................................... 3-21

Fig. 3.3.10 Structure of timer 123 mode register ............................................................................. 3-22

Fig. 3.3.11 Structure of

φ output control register ............................................................................. 3-22

Fig. 3.3.12 Structure of A-D control register .................................................................................... 3-23

Fig. 3.3.13 Structure of segment output register ............................................................................. 3-24

Fig. 3.3.14 Structure of LCD mode register ..................................................................................... 3-25

Fig. 3.3.15 Structure of interrupt edge selection register ................................................................. 3-26

Fig. 3.3.16 Structure of CPU mode register .................................................................................... 3-26

Fig. 3.3.17 Structure of interrupt request register 1 ......................................................................... 3-27

Fig. 3.3.18 Structure of interrupt request register 2 ......................................................................... 3-27

Fig. 3.3.19 Structure of interrupt control register 1 .......................................................................... 3-28

Fig. 3.3.20 Structure of interrupt control register 2 .......................................................................... 3-28

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