R8C16 datasheet(79/279 Pages) RENESAS

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R8C/16 Group, R8C/17 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 66 of 254

REJ09B0169-0210

11.1.6.7

Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack.

After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register,

extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 11.7

shows the Stack State Before and After Acknowledgement of Interrupt Request.

The other necessary registers are saved by a program at the beginning of the interrupt routine. The

PUSHM instruction can save several registers in the register bank being currently used(1) with 1

instruction.

NOTES:

1. Selectable from the R0, R1, R2, R3, A0, A1, SB and FB registers.

Figure 11.7

Stack State Before and After Acknowledgement of Interrupt Request

The register saving operation which is performed in the interrupt sequence is saved in 8 bits every 4

steps. Figure 11.8 shows Operation of Saving Register.

Figure 11.8

Operation of Saving Register

Sta c k

[SP]

S P v a lu e be fo re

in te rru p t re q u e s t is

ac k n ow le dg ed

C ontent of P rev ious S tac k

LS B

MS B

A ddres s

C ontent of P rev ious S tac k

− 4

− 3

− 2

− 1

m+ 1

S tac k s tate before in te rrupt reque s t

is ac k now ledged

[S P ]

Ne w SP Va lu e

C ontent of P rev ious S tac k

LS B

MS B

C ontent of P rev ious S tac k

m+ 1

S tac k s tate afte r in te rrupt reques t

is ac k now ledged

PC L

PC M

FL G L

FL G H

PC H

− 4

− 3

− 2

− 1

Sta c k

A ddres s

P C H

: H igh -o rd er 4 b its o f P C

P C M

: M idd le -o rd er 8 bits o f P C

P C L

: Lo w -o rde r 8 bits of P C

FLG H

: H igh -o rd er 4 b its o f F L G

FLG L

: Lo w -o rde r 8 bits of FL G

NO T E S

1.W hen ex ec uting the s o ftw are num ber 3 2 to 63 IN T in s tru c tions ,

th is S P is s p e c ifie d b y th e U fla g . O th e rw is e it is IS P .

Stack

completed saving

registers in four

operations.

Address

[SP]

−5

[SP]

PCL

PCM

FLGL

FLGH

PCH

(3)

(4)

(1)

(2)

Saved, 8 bits at a time

Sequence in which

order registers are

saved

NOTES :

1. [SP] indicates the default value of the SP when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

W hen executing the

software number 32 to 63 INT instructions, this SP is specified by the U

flag. Otherwise it is ISP.

[SP]

−4

[SP]

−3

[SP]

−2

[SP]

−1

PCH

: High-order 4 bits of PC

PCM

: Middle-order 8 bits of PC

PCL

: Low-order 8 bits of PC

FLGH

: High-order 4 bits of FLG

FLGL

: Low-order 8 bits of FLG

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