SH7101 datasheet(28/486 Pages) RENESAS

28 / 486 page

Rev.2.00 Sep. 27, 2007 Page xxviii of xxxiv

REJ09B0394-0200

Figure 11.2

Operation Example in Continuous Scan Mode

(Three Channels Selected) (AN8 to AN10) ........................................................... 334

Figure 11.3

A/D Conversion Timing......................................................................................... 336

Figure 11.4

External Trigger Input Timing ............................................................................... 337

Figure 11.5

Definitions of A/D Conversion Accuracy .............................................................. 339

Figure 11.6

Definitions of A/D Conversion Accuracy .............................................................. 339

Figure 11.7

Example of Analog Input Circuit ........................................................................... 340

Figure 11.8

Example of Analog Input Protection Circuit.......................................................... 342

Figure 11.9

Analog Input Pin Equivalent Circuit ...................................................................... 342

Section 12 Compare Match Timer (CMT)

Figure 12.1

CMT Block Diagram.............................................................................................. 343

Figure 12.2

Counter Operation.................................................................................................. 346

Figure 12.3

Count Timing ......................................................................................................... 347

Figure 12.4

CMF Set Timing .................................................................................................... 348

Figure 12.5

Timing of CMF Clear by CPU ............................................................................... 348

Figure 12.6

CMCNT Write and Compare Match Contention ................................................... 349

Figure 12.7

CMCNT Word Write and Increment Contention ................................................... 350

Figure 12.8

CMCNT Byte Write and Increment Contention..................................................... 351

Section 14 I/O Ports

Figure 14.1

Port A ..................................................................................................................... 371

Figure 14.2

Port B ..................................................................................................................... 374

Figure 14.3

Port E...................................................................................................................... 376

Figure 14.4

Port F...................................................................................................................... 379

Figure 14.5

Port G ..................................................................................................................... 381

Section 15 Mask ROM

Figure 15.1

Mask ROM Block Diagram ................................................................................... 383

Section 17 Power-Down Modes

Figure 17.1

Mode Transition Diagram ...................................................................................... 389

Figure 17.2

NMI Timing in Software Standby Mode................................................................ 398

Section 19 Electrical Characteristics

Figure 19.1

Output Load Circuit ............................................................................................... 425

Figure 19.2

System Clock Timing............................................................................................. 427

Figure 19.3

EXTAL Clock Input Timing .................................................................................. 427

Figure 19.4

Oscillation Settling Time ....................................................................................... 427

Figure 19.5

Reset Input Timing................................................................................................. 429

Figure 19.6

Reset Input Timing................................................................................................. 429

Figure 19.7

Interrupt Signal Input Timing................................................................................. 430

Figure 19.8

Interrupt Signal Output Timing.............................................................................. 430

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