SH7059 datasheet(21/1042 Pages) RENESAS

21 / 1042 page

Differences between SH7058 and SH7058S/SH7059

Rev.3.00 Mar. 12, 2008 Page xxi of xc

REJ09B0177-0300

SH7058 (Rev.3, REJ09B0046-0300H)

SH7058S/SH7059

15.2.6 Serial Control Register (SCR)

472

The CPU can always read and write to SCR. SCR is

initialized to H'00 by a power-on reset and in hardware

standby mode. It is not initialized by a manual reset and in

software standby mode.

15.2.6 Serial Control Register (SCR)

Description amended

The CPU can always read/write to SCR.

SCR is

initialized to H'00 by a power-on reset and in hardware

standby mode. The value is not retrained in software

standby mode and it is initialized after release. It is not

initialized by a manual reset.

15.2.8 Bit Rate Register (BRR)

480

The CPU can always read and write to BRR. BRR is

initialized to H'FF by a power-on reset and in hardware

standby mode. It is not initialized by a manual reset and in

software standby mode. Each channel has independent

baud rate generator control, so different values can be set

for each channel.

15.2.8 Bit Rate Register (BRR)

Description amended

The CPU can always read

to BRR. The CPU should only

perform write operations when making initial settings. Do

not use the CPU to perform writes during transmit, receive,

or transmit/receive operation. BRR is initialized to H'FF by

a power-on reset and in hardware standby mode. The

value is not retained in software standby mode and it is

initialized after release. It is not initialized by a manual

reset

. Each channel has independent baud rate

generator control, so different values can be set for each

channel.

15.2.9 Serial Direction Control Register (SDCR)

487

The description in this section assumes LSB-first transfer.

SDCR is initialized to H'F2 by a power-on reset and in the

hardware standby mode. It is not initialized by a manual

reset and in software standby mode.

15.2.9 Serial Direction Control Register (SDCR)

Description amended

The description in this section assumes LSB-first transfer.

The CPU can always read from SDCR. The CPU should

only write to SDCR when making initial settings. Do not use

the CPU to write to SDCR during transmit, receive, or

transmit/receive operation.

SDCR is initialized to H'F2 by a power-on reset and in the

hardware standby mode. The value is not retained in

software standby mode and it is initialized after release. It

is not initialized by a manual reset

15.3.2 Operation in Asynchronous Mode

SCI Initialization (Asynchronous Mode):

Figure 15.5 Sample Flowchart for Transmitting Serial Data

494

Clear TE bit in SCR to 0;

select theTxD pin as an

output port with the PFC

15.3.2 Operation in Asynchronous Mode

SCI Initialization (Asynchronous Mode):

Figure 15.5 Sample Flowchart for Transmitting Serial Data

Figure amended and note added

Clear TE bit in SCR to 0;

select theTxD pin as an

output port with the PFC

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a transmit operation. However, this

does not apply to operation 5.

Receiving Serial Data (Asynchronous Mode):

Figure 15.7 Sample Flowchart for Receiving Serial Data (1)

497

Clear RE bit in SCR to 0

Receiving Serial Data (Asynchronous Mode):

Figure 15.7 Sample Flowchart for Receiving Serial Data (1)

Figure amended and note added

Clear RE bit in SCR to 0

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a receive operation. However, this

does not apply to operation 5.

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