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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7727 датащи(PDF) 13 Page - Renesas Technology Corp |
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SH7727 датащи(HTML) 13 Page - Renesas Technology Corp |
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13 / 1109 page  Rev. 5.00 Dec 12, 2005 page xiii of lxxii Page Previous Version Revised Version 303 12.2.5 Individual Memory Control Register (MCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPC1 TPC0 RCD1 RCD0 TRWL 1 TRWL 0 TRAS 1 TRAS 0 RASD AMX3 AMX2 AMX1 AMX0 RFSH RMO DE — Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9876543210 TPC1 TPC0 RCD1 RCD0 TRWL 1 TRWL 0 TRAS 1 TRAS 0 — AMX3 AMX2 AMX1 AMX0 RFSH RMO DE — Initial value: 0000000000000000 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 and 14 RAS Precharge Time (TPC1, TPC0): … However, the number of cycles inserted immediately after the precharge all banks (PALL) command is issued when performing auto-refresh or the precharge (PRE) command is issued in bank-active mode is one fewer than the number of cycles during normal operation. Do not set TPC1 to 0 and TPC0 to 0 when in bank- active mode. … However, the number of cycles inserted immediately after the precharge all banks (PALL) command is issued when performing auto-refresh is one fewer than the number of cycles during normal operation. Note: * Immediately after the precharge all banks (PALL) command is issued when performing auto-refresh or the precharge (PRE) command is issued in bank-active mode. Note: * Immediately after the precharge all banks (PALL) command is issued when performing auto-refresh. 304 Bit 7—SDRAM Bank Active (RASD): Specifies whether SDRAM is put into bank- active mode or auto-precharge mode. The auto-precharge mode should be used if both area 2 and area 3 are set in SDRAM space and the bus width is 16 bits. Bit 7: RASD Description 0 Auto-precharge mode (Initial value) 1 Bank-active mode Bit 7 Reserved: This bit is always read as 0. The write value should always be 0. Table deleted 309 12.2.6 PCMCIA Control Register (PCR) Bits 8, 1, and 0 Area6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, and A6TEH0): Bit 8: A6TEH2 Bit 1: A6TEH1 Bit 0: A6TEH0 Description 1004.5-cycle delay 1 Reserved 1 0 Reserved 1 Reserved Bit 8: A6TEH2 Bit 1: A6TEH1 Bit 0: A6TEH0 Description 1004.5-cycle delay 1 5.5-cycle delay 10 6.5-cycle delay 1 7.5-cycle delay |
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