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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/86T датащи(PDF) 191 Page - Renesas Technology Corp |
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M32C/86T датащи(HTML) 191 Page - Renesas Technology Corp |
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191 / 505 page  Page 168 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 15. Timer (Timer B) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Timer Bi Mode Register (i=0 to 5) (Event Counter Mode) Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 RW RW RW RW RW RW RW RW TMOD0 TMOD1 MR0 Operating Mode Select Bit MR1 MR3 MR2 TCK0 TCK1 Event Clock Select Bit 0 : Input signal from the TBiIN pin 1 : TBj overflows or underflows(2) TB0MR and TB3MR registers: Set to "0" in event counter mode Disabled in event counter mode. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. Can be set to "0" or "1". Count Polarity Select Bit(1) 0 1 : Event counter mode b1b0 Bit Name Function Bit Symbol 0 0 : Counts falling edges of external signal 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges of external signal 1 1 : Do not set to this value b3b2 NOTES: 1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1". 2. j = i-1, except j = 2 when i = 0 and j = 5 when i = 3. TB1MR, TB2MR, TB4MR and TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 00 1 Figure 15.21 TB0MR to TB5MR Registers |
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