M32CSLASH86 datasheet(166/505 Pages) RENESAS

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Page 143

14. DMACII

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14.8 Execution Time

DMAC II execution cycle is calculated by the following equations:

Multiple transfers: t = 21+ (11 + b + c) x k cycles

Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles

a: If IMM = 0 (source of transfer is immediate data), a = 0;

if IMM = 1 (source of transfer is memory), a = –1

b: If UPDS = 1 (source transfer address is a relocatable address), b = 0;

if UPDS = 0 (source transfer address is a fixed address), b = 1

c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0;

if UPDD = 0 (destination transfer address is a fixed address), c = 1

d: If OPER = 0 (calculation function is not selected), d = 0;

if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed

address memory), d = 7;

if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address

memory), d = 8

e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4

m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in transfer counter

n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1

k: Number of transfers set in the CNT2 to CNT0 bits

The equations above are approximations. The number of cycles may vary depending on CPU state, bus

wait state, and DMAC II index allocation.

The first instruction from the end-of-transfer interrupt routine is executed in the eighth cycle after the DMAC

II transfer is completed.

Figure 14.5 Transfer Cycle

When an interrupt request as a DMAC II transfer request source and another interrupt request with higher

_______

priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes

precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence

has been completed.

a=-1

b=0

c=1

d=0

e=0

m=1

First DMAC II transfer

t=6+26x1+4x1=36 cycles

Second DMAC II transfer t=6+26x1+4x0=32 cycles

Transfer counter = 2

Decrement a transfer counter

Transfer counter = 1

Program

DMAC II transfer

(First time)

DMAC II transfer

(Second time)

cycles

Processing the end-of-transfer

interrupt

DMAC II transfer request

Decrement a transfer counter

Transfer counter = 0

cycles

DMAC II transfer request

If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function

after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address,

single transfer and double transfer:

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