M32CSLASH86 datasheet(165/505 Pages) RENESAS

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Page 142

14. DMACII

)

(

14.6 Chained Transfer

The CHAIN bit in MOD selects the chained transfer.

The following process initiates the chained transfer.

(1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index.

The vectors of the request source indicates where the DMAC II index is allocated. For each request, the

BRST bit selects either single or burst transfer.

(2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request

source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simulta-

neously.

(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the

DMAC II index indicated by the peripheral function interrupt vector rewritten in (2).

Figure 14.4 shows the relocatable vector and DMACII index when the chained transfer is in progress.

For the chained transfer, the relocatable vector table must be located in the RAM.

RAM

Relocatable Vector

INTB

DMAC II

Index(1)

DMAC II

Index(2)

BASE(1)

BASE(2)

BASE(3)

(CADR1 to

CADR0)

(CADR1 to

CADR0)

Peripheral I/O interrupt vector causing DMAC II request

Default value of DMAC II is BASE(1).

The above vector is rewritten to BASE(2)

when a transfer is completed.

The above vector is rewritten to BASE(3)

when a transfer is completed.

Starts at BASE(2) when next request conditions

are met.

Transferred according to the DMAC II Index.

Figure 14.4 Relocatable Vector and DMAC II Index

14.7 End-of-Transfer Interrupt

The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer

interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0."

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