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H8SX1663 датащи(PDF) 120 Page - Renesas Technology Corp

номер детали H8SX1663
подробное описание детали  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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Section 3 MCU Operating Modes
Rev.1.00 Jun. 07, 2006 Page 68 of 1102
REJ09B0294-0100
3.2.2
System Control Register (SYSCR)
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit
Bit Name
Initial Value
R/W
Note: * The initial value depends on the startup mode.
15
1
R/W
14
1
R/W
13
MACS
0
R/W
12
1
R/W
11
FETCHMD
0
R/W
10
Undefined*
R
9
EXPE
Undefined*
R/W
8
RAME
1
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
DTCMD
1
R/W
0
1
R/W
Bit
Bit Name
Initial
Value
R/W
Descriptions
15
14
1
1
R/W
R/W
Reserved
These bits are always read as 1. The write value should
always be 1.
13
MACS
0
R/W
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
12
1
R/W
Reserved
This bit is always read as 1. The write value should
always be 1.
11
FETCHMD 0
R/W
Instruction Fetch Mode Select
This LSI can prefetch an instruction in units of 16 bits or
32 bits. Select the bus width for instruction fetch
depending on the used memory for the storage of
programs*
1.
0: 32-bit mode
1: 16-bit mode



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