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M32C/8B датащи(PDF) 127 Page - Renesas Technology Corp |
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M32C/8B датащи(HTML) 127 Page - Renesas Technology Corp |
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127 / 406 page ![]() Under development M32C/8B Group 11. Interrupts Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 110 of 385 Figure 11.10 Interrupt Priority Level Decision Circuit DMA1 DMA2 DMA3 Timer A0 UART0 transmission/NACK UART0 reception/ACK UART1 transmission/NACK Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT2 INT1 INT0 Timer B5 UART2 transmission/NACK UART2 reception/ACK IPL I flag DMA0 Timer A3 Timer A4 Watchdog timer, oscillation stop detection, voltage monitor NMI DMACII Interrupt request acknowledged (to CPU) Level 0 (initial value) Interrupt priority level High Low Peripheral function interrupt priority (if priority levels are the same) Timer A1 Timer A2 UART1 reception/ACK Timer B0 INT3 UART3 transmission/NACK Address match UART3 reception/ACK UART4 transmission/NACK UART4 reception/ACK Bus conflict/ start or stop condition detection (UART2) Bits RLVL2 to RLVL0 Bus conflict/ start or stop condition detection (UART0, UART3) Key input interrupt A/D0 Bus conflict/ start or stop condition detection (UART1, UART4) Interrupt priority level Request signal used to wake-up from wait mode/stop mode (to the clock generation circuit) |
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