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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 106 of 385

11.6.3

Interrupt Sequence

The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine

execution.

When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt

priority after the instruction in progress is completed. Then, the CPU starts the interrupt sequence from the

following cycle. However, for the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT, and RMPA

instructions, if an interrupt request is generated while one of these instructions is being executed, the MCU

suspends the instruction execution to start the interrupt sequence.

The interrupt sequence is performed as indicated below:

(1) The CPU obtains the interrupt number by reading the address 000000h (address 000002h for the high-

speed interrupt). Then, the corresponding IR bit to the interrupt becomes 0 (interrupt not requested).

(2) The FLG register value, immediately before the interrupt sequence, is saved to a temporary register(1) in

the CPU.

(3) Each bit in the FLG register becomes as follows:

The I flag becomes 0 (interrupt disabled)

The D flag becomes 0 (single-step interrupt disabled)

The U flag becomes 0 (ISP selected)

(4) The internal register value (the FLG register value saved in (2)) in the CPU is saved to the stack; or to

the SVF register for the high-speed interrupt.

(5) The PC value is saved to the stack; or to the SVP register for the high-speed interrupt.

(6) The interrupt priority level of the acknowledged interrupt becomes the IPL level.

(7) An interrupt vector corresponding to the acknowledged interrupt is stored into PC.

After the interrupt sequence is completed, the CPU executes the instruction from the starting address of the

interrupt routine.

NOTE:

1. Temporary register cannot be accessed by users.

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