SH7672 datasheet(22/1292 Pages) RENESAS

22 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xxii of xxvi

20.4.1

HIF Index Register (HIFIDX) .......................................................................... 880

20.4.2

HIF General Status Register (HIFGSR)............................................................ 882

20.4.3

HIF Status/Control Register (HIFSCR) ............................................................ 883

20.4.4

HIF Memory Control Register (HIFMCR) ....................................................... 886

20.4.5

HIF Internal Interrupt Control Register (HIFIICR) .......................................... 888

20.4.6

HIF External Interrupt Control Register (HIFEICR) ........................................ 889

20.4.7

HIF Address Register (HIFADR) ..................................................................... 890

20.4.8

HIF Data Register (HIFDATA) ........................................................................ 891

20.4.9

HIF Boot Control Register (HIFBCR).............................................................. 891

20.4.10

HIFDREQ Trigger Register (HIFDTR) ............................................................ 893

20.4.11

HIF Bank Interrupt Control Register (HIFBICR) ............................................. 894

20.5

Memory Map .................................................................................................................... 896

20.6

Interface ............................................................................................................................ 897

20.6.1

Basic Sequence ................................................................................................. 897

20.6.2

Reading/Writing of HIF Registers other than HIFIDX and HIFIDX ............... 898

20.6.3

Consecutive Data Writing to HIFRAM by External Device............................. 899

20.6.4

Consecutive Data Reading from HIFRAM to External Device ........................ 900

20.7

External DMAC Interface................................................................................................. 901

20.8

Alignment Control ............................................................................................................ 906

20.9

Interface When External Device Power is Cut Off ........................................................... 907

Section 21 Compare Match Timer (CMT) ........................................................ 911

21.1

Features............................................................................................................................. 911

21.2

Register Descriptions........................................................................................................ 912

21.2.1

Compare Match Timer Start Register (CMSTR) .............................................. 913

21.2.2

Compare Match Timer Control/Status Register (CMCSR) .............................. 914

21.2.3

Compare Match Counter (CMCNT) ................................................................. 916

21.2.4

Compare Match Constant Register (CMCOR) ................................................. 916

21.3

Operation .......................................................................................................................... 917

21.3.1

Interval Count Operation .................................................................................. 917

21.3.2

CMCNT Count Timing..................................................................................... 917

21.4

Interrupts........................................................................................................................... 918

21.4.1

Interrupt Sources and DMA Transfer Requests ................................................ 918

21.4.2

Timing of Compare Match Flag Setting ........................................................... 918

21.4.3

Timing of Compare Match Flag Clearing......................................................... 919

21.5

Usage Notes ...................................................................................................................... 920

21.5.1

Conflict between Write and Compare-Match Processes of CMCNT ............... 920

21.5.2

Conflict between Word-Write and Count-Up Processes of CMCNT ............... 921

21.5.3

Conflict between Byte-Write and Count-Up Processes of CMCNT................. 922

21.5.4

Compare Match Between CMCNT and CMCOR ............................................ 922

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