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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618A датащи(PDF) 282 Page - Renesas Technology Corp |
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HD6417618A датащи(HTML) 282 Page - Renesas Technology Corp |
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282 / 646 page  Section 11 Ethernet Controller (EtherC) Rev. 6.00 Jun. 12, 2007 Page 250 of 610 REJ09B0131-0600 1. When the receive enable (RE) bit is set, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. Discards a frame with an invalid pattern. 3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast or multicast transmission or promiscuous mode is specified, the receiver starts data reception. 4. Following data reception from the MII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to memory. Reports an error status in the case of an abnormality. 5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode register, the receiver prepares to receive the next frame. 11.4.3 MII Frame Timing Each MII Frame timing is shown in figure 11.4. TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL SFD Preamble Data CRC Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission) TX-CLK TX-EN TX-ER CRS COL Preamble JAM MII_TXD3 to MII_TXD0 Figure 11.4 (2) MII Frame Transmit Timing (Collision) |
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