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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6417618A датащи(PDF) 351 Page - Renesas Technology Corp |
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HD6417618A датащи(HTML) 351 Page - Renesas Technology Corp |
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351 / 646 page  Section 13 Compare Match Timer (CMT) Rev. 6.00 Jun. 12, 2007 Page 319 of 610 REJ09B0131-0600 13.3 Operation 13.3.1 Interval Count Operation When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 13.2 shows the operation of the compare match counter. CMCOR1 H'0000 CMCNT1 value Time Counter cleared by compare match with CMCOR1 Figure 13.2 Counter Operation 13.3.2 CMCNT Count Timing One of four internal clocks (P φ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 13.3 shows the timing. Peripheral operating clock (P φ) Nth clock (N + 1)th clock Count clock CMCNT1 N N + 1 Figure 13.3 Count Timing |
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