HD64F2145B datasheet(13/845 Pages) RENESAS

номер детали	HD64F2145B

подробное описание детали	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	845 Pages

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производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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13 / 845 page

Rev. 3.00 Mar 21, 2006 page xiii of liv

Item

Page

Revision (See Manual for Details)

16.3.5 I

2C Bus

427, 428 Table amended

Bit 1 R/W of I

2C Bus Interface Interrupt Request Flag

(Before) R/W

→ (After) R/(W)*

Table 16.5 Flash and

Transfer States (Slave

Mode)

430

Table 16.5 amended

MST

TRS

BBSY ESTP STOP IRTR

AASX AL

AAS

ADZ

ACKB ICDRF ICDRE State

011001

↑/0*2 ———

—

↑

Transmission end with

ICDRE = 0

01100

——

↓

—

↓

ICDR write with the

above state

01100

————

—

Transmission end with

ICDRE = 1

01100

——

↓

—

↓

ICDR write with the

above state

011001

↑/0*2 —

0000

—

↑

Automatic data transfer

from ICDRT to ICDRS

with the above state

16.4.4 Master

Receive Operation

Figure 16.12 Example

of Operation Timing in

Master Receive Mode

(MLS = WAIT = 0,

HNDS = 1)

451

Figure 16.12 amended

SDA

(master output)

SDA

(slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

IRTR

ICDRF

ICDRR

SCL

(master output)

Master transmit mode

Master receive mode

Data 1

[1] TRS = 0 clear

[2] ICDR read

(Dummy read)

[1] IRIC clear

SCL is fixed low until ICDR is read

User processing

IRIC

Undefined va

Figure 16.13 Example

of Stop Condition

Issuance Operation

Timing in Master

Receive Mode (MLS =

WAIT = 0, HNDS = 1)

451

Figure 16.13 amended

Bit 1

Data 3

[9] IRIC clear

[8]

[11] Set BBSY = 0 and

SCP = 0

(Stop condition instruction issuance)

[10] ICDR read

(Data 3)

Bit 0

Stop condition generation

SCL is fixed low until

stop condition is issued

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