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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H83802 датащи(PDF) 73 Page - Renesas Technology Corp |
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H83802 датащи(HTML) 73 Page - Renesas Technology Corp |
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73 / 555 page  Section 2 CPU CPU30L0A_000020020900 Rev. 6.00 Mar 15, 2005 page 23 of 502 REJ09B0024-0600 Section 2 CPU The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1 Features • General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit registers • Fifty-five basic instructions Multiply and divide instructions Powerful bit-manipulation instructions • Eight addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with displacement [@(d:16,Rn)] Register indirect with post-increment or pre-decrement [@Rn+ or @–Rn] Absolute address [@aa:8 or @aa:16] Immediate [#xx:8 or #xx:16] Program-counter relative [@(d:8,PC)] Memory indirect [@@aa:8] • 64-kbyte address space • High-speed operation All frequently-used instructions execute in two to four states 8/16-bit register-register add/subtract : 0.25 µs* 8 × 8-bit multiply : 1.75 µs* 16 ÷ 8-bit divide : 1.75 µs* Note: * These values are at φ = 8 MHz. • Power-down state Transition to power-down state by SLEEP instruction |
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