M32C87 datasheet(86/627 Pages) RENESAS

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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)

8. Bus

REJ09B0180-0151 Rev.1.51 Jul 31, 2008

Page 64 of 587

8.1.1

Selecting External Address Bus

The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space

(CS area) vary in each external space mode. Bits PM11 and PM10 in the PM1 register select external space

mode.

8.1.2

Selecting External Data Bus

The DS register selects either external 8-bit data bus or 16-bit data bus per each external space. The data bus in

the external space 3 becomes 16 bits wide when a low-level (“L”) signal is applied to the BYTE pin after reset,

and 8 bits wide when a high-level (“H”) signal is applied. Do not change the BYTE pin level while the MCU is

operating. Internal bus is always 16 bits wide.

8.1.3

Selecting Separate Bus/Multiplexed Bus

Bits PM05 and PM04 in the PM0 register select either the separate bus or multiplexed bus. The MCU starts up

with the separate bus after reset.

8.1.3.1

Separate Bus

With the separate bus format, the MCU performs data input/output and address output using individual buses.

The DS register selects 8-bit or 16-bit external data bus for each external space. If all DSi bits in the DS register

(i = 0 to 3) are set to 0 (8-bit data bus), port P0 functions as the data bus and port P1 as the programmable I/O

port.

If any of the DSi bits is set to 1 (16-bit data bus), ports P0 and P1 function as the data bus. Port P1 output is

undefined when the MCU accesses the space where its DSi bit is set to 0.

8.1.3.2

Multiplexed Bus

With the multiplexed bus format, the MCU performs data input/output and address output using the same bus

by time-sharing. D0 to D7 are time-multiplexed with A0 to A7 in the space accessed by the 8-bit data bus. D0 to

D15 are time-multiplexed with A0 to A15 in the space accessed by the 16-bit data bus.

When bits PM05 and PM04 in the PM0 register are set to 11b (access all CS area using multiplexed bus),

address bus has only 16 bits using A0 to A15. In this case, the accessible space is 64 Kbytes per each chip-select

output. Refer to Table 8.3 Processor Mode and Pin Function for details.

Table 8.2 lists multiplexed bus settings and chip-select areas.

Table 8.2

Multiplexed Bus Settings and Chip-Select Areas

NOTE:

1. In microprocessor mode, do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using

multiplexed bus).

PM05 and PM04

bits setting

PM11 and PM10 Bits Setting

00b

(external space

mode 0

01b

(external space

mode 1)

10b

(external space

mode 2)

11b

(external space

mode 3)

00b

(multiplexed bus not used)

Separate bus

01b

(access the CS2 area

using multiplexed bus)

Do not set to

these values

CS2

Do not set to

this value

CS2

10b

(access the CS1 area

using multiplexed bus)

CS1

11b

(access the all CS areas

using multiplexed bus)(1)

CS0

CS1

CS2

CS0

CS1

CS0

CS1

CS2

CS3

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