R8C2K datasheet(274/471 Pages) RENESAS

274 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 257 of 450

REJ09B0406-0110

Figure 16.98

Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi

Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin

Set to 0 by a program

Value in TRDi register

Count source

TRDIOAi output

FFFFh

TRDIOBi output

m: Value set in TRDGRAi register

n: Value set in TRDGRCi register

p: Value set in TRDGRBi register

q: Value set in TRDGRDi register

The above applies under the following conditions:

The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).

Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register).

Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs).

Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register).

Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output “L” to compare match).

Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).

Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match).

Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match).

Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).

i = 0 or 1

m+1

n+1

0000h

m-n

p+1

p-q

q+1

IMFA bit in

TRDSRi register

IMFC bit in

TRDSRi register

Set to 0 by a program

Output inverted by compare match

Initial output “L”

IMFB bit in

TRDSRi register

IMFD bit in

TRDSRi register

Initial output “L”

Set to 0 by a program

Output inverted by compare match

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