R8C2K datasheet(125/471 Pages) RENESAS

125 / 471 page

R8C/2K Group, R8C/2L Group

12. Interrupts

Rev.1.10

Dec 21, 2007

Page 108 of 450

REJ09B0406-0110

12.1.6.7

Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack.

After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG

Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.

The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM

instruction can save several registers in the register bank being currently used(1) with a single instruction.

NOTE:

1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.

Figure 12.8

Stack State Before and After Acknowledgement of Interrupt Request

The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in

four steps.

Figure 12.9 shows the Register Saving Operation.

Figure 12.9

Stack

[SP]

SP value before

interrupt is generated

Previous stack contents

LSB

MSB

Address

Previous stack contents

−4

−3

−2

−1

m+1

Stack state before interrupt request

is acknowledged

[SP]

New SP value

Previous stack contents

LSB

MSB

Previous stack contents

m+1

Stack state after interrupt request

is acknowledged

PCL

PCM

FLGL

FLGH

PCH

−4

−3

−2

−1

Stack

Address

PCH

: 4 high-order bits of PC

PCM

: 8 middle-order bits of PC

PCL

: 8 low-order bits of PC

FLGH

: 4 high-order bits of FLG

FLGL

: 8 low-order bits of FLG

NOTE:

1.When executing software number 32 to 63 INT instructions,

this SP is specified by the U flag. Otherwise it is ISP.

Stack

Completed saving

registers in four

operations.

Address

[SP]

−5

[SP]

PCL

PCM

FLGL

FLGH

PCH

(3)

(4)

(1)

(2)

Saved, 8 bits at a time

Sequence in which

order registers are

saved

NOTE:

1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

When executing

software number 32 to 63 INT instructions, this SP is specified by the U

flag. Otherwise it is ISP.

[SP]

−4

[SP]

−3

[SP]

−2

[SP]

−1

PCH

: 4 high-order bits of PC

PCM

: 8 middle-order bits of PC

PCL

: 8 low-order bits of PC

FLGH

: 4 high-order bits of FLG

FLGL

: 8 low-order bits of FLG

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