M37280EKSP datasheet(9/179 Pages) RENESAS

9 / 179 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37280MF–XXXSP, M37280MK–XXXSP

M37280EKSP

MITSUBISHI MICROCOMPUTERS

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

Rev. 1.0

Table 11.2 Pin Description (continued)

Note : As shown in the memory map (Figure 12.2.1), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register

(address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register

are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port

latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-

output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float,

so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

Input/

Output

Output port P5

PWM output

OSD output

Output port P6

Input port P6

Clock input for OSD

Clock output for OSD

Sub-clock output

Sub-clock input

Input port P7

Input for data

slicer

Serial I/O data input

Analog input

HSYNC input

VSYNC input

Port P5 is a 4-bit output port. The output structure of P50, P51, P56 and P57 is N-channel

open-drain output, that of P52–P55 is CMOS output.

Pin P50 is also used as 8-bit PWM output pin PWM7. The output structure is N-channel

open-drain output.

Pins P52–P55 are also used as OSD output pins R/R1, G/G1, B/B1, OUT1 respectively. At

R, G, B output, the output structure is analog output. At R1, G1, B1 and OUT1 output, the

output structure is CMOS output.

Ports P60–P62 and P65–P67 are 6-bit output ports. The output structure is N-channel open-

drain output.

Ports P63 and P64 are 2-bit input port.

Pin P63 is also used as OSD clock input pin OSC1.

Pin P64 is also used as OSD clock output pin OSC2. The output structure is CMOS output.

Pin P64 is also used as sub-clock output pin XCOUT. The output structure is CMOS output.

Pin P63 is also used as sub-clock input pin XCIN.

Ports P70–P72 are 3-bit input port.

Pins P70, P71 are also used as data slicer input pins CVIN, VHOLD respectively. When using

data slicer, input composite video signal through a capacitor. Connect a capacitor between

VHOLD and VSS.

Pins P72 is also used as serial I/O data input pin SIN.

When using data slicer, connect a filter using of a capacitor and a resistor between HLF and

VSS.

This is an analog input pin AD6 .

This is a horizontal synchronous signal input for OSD.

This is a vertical synchronous signal input for OSD.

Name

Functions

Output

Input

Output

Input

P70/CVIN,

P71/VHOLD,

P72/(SIN)

HLF/AD6

HSYNC

VSYNC

P60–P62,

P65–P67

P63/OSC1/

XCIN,

P64/OSC2/

XCOUT

P50/PWM7,

P51,

P52/R/R1,

P53/G/G1,

P54/B/B1,

P55/OUT1,

P56, P57

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