M37270MF datasheet(13/95 Pages) RENESAS

13 / 95 page

MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

INTERRUPTS

Interrupts can be caused by 18 different sources consisting of 4 ex-

ternal, 12 internal, 1 software, and reset. Interrupts are vectored in-

terrupts with priorities shown in Table 1. Reset is also included in the

table because its operation is similar to an interrupt.

When an interrupt is accepted,

(1) The contents of the program counter and processor status

(2) The interrupt disable flag I is set to “1” and the corresponding

interrupt request bit is set to “0.”

(3) The jump destination address stored in the vector address enters

the program counter.

Other interrupts are disabled when the interrupt disable flag is set to

“1.”

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit. The interrupt request bits are

in interrupt request registers 1 and 2 and the interrupt enable bits are

in interrupt control registers 1 and 2. Figure 5 shows the structure of

the interrupt-related registers.

Interrupts other than the BRK instruction interrupt and reset are ac-

cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”

and the interrupt disable flag is “0.” The interrupt request bit can be

set to “0” by a program, but not set to “1.” The interrupt enable bit can

be set to “0” and “1” by a program.

Reset is treated as a non-maskable interrupt with the highest priority.

Figure 6 shows interrupt control.

Interrupt Causes

(1) VSYNC and OSD interrupts

The VSYNC interrupt is an interrupt request synchronized with

the vertical sync signal.

The OSD interrupt occurs after character block display to the

CRT is completed.

(2) INT1, INT2, INT3 interrupts

With an external interrupt input, the system detects that the level

of a pin changes from “L” to “H” or from “H” to “L,” and generates

an interrupt request. The input active edge can be selected by

bits 3, 4 and 6 of the interrupt interval determination control reg-

ister (address 021216) : when this bit is “0,” a change from “L” to

“H” is detected; when it is “1,” a change from “H” to “L” is de-

tected. Note that all bits are cleared to “0” at reset.

(3) Timer 1, 2, 3 and 4 interrupts

An interrupt is generated by an overflow of timer 1, 2, 3 or 4.

(4) Serial I/O interrupt

This is an interrupt request from the clock synchronous serial

I/O function.

(5) f(XIN)/4096 interrupt

This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0

of the PWM mode register 1 to “0.”

(6) Data slicer interrupt

An interrupt occurs when slicing data is completed.

(7) Multi-master I2C-BUS interface interrupt

This is an interrupt request related to the multi-master I2C-BUS

interface.

(8) A-D conversion interrupt

An interrupt occurs at the completion of A-D conversion. Since

A-D conversion interrupt and the INT3 interrupt share the same

vector, an interrupt source is selected by bit 7 of the interrupt

interval determination control register (address 021216).

Vector addresses

FFFF16, FFFE16

FFFD16, FFFC16

FFFB16, FFFA16

FFF916, FFF816

FFF716, FFF616

FFF516, FFF416

FFF316, FFF216

FFF116, FFF016

FFEF16, FFEE16

FFED16, FFEC16

FFEB16, FFEA16

FFE916, FFE816

FFE716, FFE616

FFE516, FFE416

FFE316, FFE216

FFDF16, FFDE16

Interrupt source

Reset

OSD interrupt

INT1 interrupt

Data slicer interrupt

Serial I/O interrupt

Timer 4 interrupt

f(XIN)/4096 interrupt

VSYNC interrupt

Timer 3 interrupt

Timer 2 interrupt

Timer 1 interrupt

A-D convertion · INT3 interrupt

INT2 interrupt

Multi-master I2C-BUS interface interrupt

Timer 5 · 6 interrupt

BRK instruction interrupt

Remarks

Non-maskable

Active edge selectable

Non-maskable (software interrupt)

Table 1. Interrupt vector addresses and priority

Priority

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