STV9432TA

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V1 Register: V sync to Active video, min. of K to A

V2 Register: Active video to V sync, min. of B to K’

V3 Register: Number of lines per frame, K to K’7

7.3 - Timing Analysis Trigger

The Timing Analysis is performed according to the setting of SBN and TIMG registers :

7.3.1 - SBN Register

This 8 bits register holds the "sampling bloc" number.

The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or

Beam currents.

The reset value of this register is zero, must be programmed at a minimum value of 1 for correct operation.

7.3.2 - TIMG Register

This 8 bits register holds the following parameters:

To initiate a Timing Analysis cycle:

- program the Sampling Bloc Number in the SBN Register,

- program the TIMG Register, with: "SELECT" bit =1, "NFR" bits specify the number of measurement frames

(H1, H2, V1, V2), "STM" bit = 1 (Start Measurement).

As soon as the measurement cycle is finished, the "STM" bit is automatically reset by the device.

After a Timing Analysis cycle, reading a zero in STM bit of TIMG register means that the measurement is com-

pleted and the MCU may read the results in Hi and Vi registers. The reset value of this register is 0.

400C

V1.7

V1.6

V1.5

V1.4

V1.3

V1.2

V1.1

V1.0

400D

-

-

-

-

V1.11

V1.10

V1.9

V1.8

400E

V2.7

V2.6

V2.5

V2.4

V2.3

V2.2

V2.1

V2.0

400F

-

-

-

-

V2.11

V2.10

V2.9

V2.8

4010

V3.7

V3.6

V3.5

V3.4

V3.3

V3.2

V3.1

V3.0

4011

-

-

-

-

V3.11

V3.10

V3.9

V3.8

4015

SBN7

SBN6

SBN5

SBN4

SBN3

SBN2

SBN1

SBN0

4016

STM

NFR1

NFR0

ADCDLY3

ADCDLY2

ADCDLY1

0

SELECT

STM

:

sequence, depending on the measurement selection bit. When measurement is com-

pleted the IC will reset this bit to 0.

NFR [1:0]

:

NFR number of measurement frames, 1 to 4 frames

ADCDLY[3:1]

:

SELECT

:

Selection of Beam current measurement (0) or Timing measurement (1)

3