IAGCS (Internal AGC Control Value)

Address

: 16

Type

: R

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IAGC-CTRL

Indicates the value of the internal AGC control signal.

Normally, the mean value should equal the value set in the IAGCR register when a signal is being

demodulated.

FFFIXL (Clock Generator Fine frequency)

Address

: 17

Type

: R/W

Reset

: 0000 0000

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

CLOCK GENERATOR FINE FREQUENCY (8 LSB’s)

See FCFIX register for explanation.

FFFIXH (Clock Generator and Fine Frequency Control)

Address

: 18

Type

: R/W

Reset

: 0110 1110

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

DEMOD MODE M2:M0

CLOCK GEN FINE FREQ (4 MSB’s)

DEMOD MODE M2:M0

: Controls the demodulator mode (only when register Ehex bits[3:0] = 0000) :

MODE[6:4]

CH1 FM

CH2 FM/QPSK

X00

Normal

FM Normal

X01

Wide

FM Wide

010

Normal

QPSK System B/G/L

011

Wide

QPSK System B/G/L

110

Normal

QPSK System I

111

Wide

QPSK System I

The FM discriminator modulation full range can be set at :

- narrow mode : 250kHz (

± 125kHz),

- wide mode : 500kHz (

± 250kHz).

CLOCK GEN FINE FREQ : Clock generator fine frequency (4 MSB’s) ( see FCFIX for explanation).

FCFIX (Clock Generator Coarse Frequency)

Address

: 19

Type

: R/W

Reset

: 0001 0001

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

0

0

CLOCK GENERATOR COARSE FREQUENCY

The bits [5:0] together with FFFIXH bits [3:0] and FFFIXL bits [7:0] can be used to programme the internal

clock generator for different quartz crystal frequencies ; the default value is for 27MHz.

P

= 182 ⋅

Fref

Fqpsk

− 193 with Fref = crystal frequency, Fqpsk = 32 x 728kHz = 23.296MHz.

FCFIX = INT(P)

(INT: integer part)

FFFIX = 256 x (16 x REM(P) - 1)

(REM: fractional remainder)

Note that 0

≤ FFFIX <3840 so there is a small range of frequencieswhich cannot be used.

Example : Fref = 27MHz, FCFIX = 17, FFFIX = 3584.

PROGRAMMING THE DEVICE (continued)

STV8203

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