STV6886 datasheet(29/43 Pages) STMICROELECTRONICS

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STV6886

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2.7 Horizontal Moiré Output

The Horizontal Moiré output is intended to correct

a beat between the horizontal video pixel period

and the CRT pixel width.

The Moiré signal is a combination of the horizontal

and vertical frequency signals.

To achieve a Moiré cancellation, the Moiré output

has to be connected so as to modulate the hori-

zontal position. We recommend introducing this

“Horizontal Controlled Jitter” on the ground side of

PLL2 capacitor where this “controlled jitter” will di-

rectly affect the horizontal position.

The amplitude of the signal is I2C adjustable. The

H-Moiré frequency can be chosen via the I2C.

If H Scanning and EHT are separated, bit D8 in

subaddress 11 should be set to 0. If H Scanning

and EHT are combined, setting this bit to 1 will pro-

vide a better screen aspect.

The H-Moiré output is combined with the PLL1

horizontal unlock output.

If HMoiré/HLock is selected (bit 02D8 to 1):

– when PLL1 is unlocked, pin 3 output voltage

goes above 6V.

– when PLL1 is locked, the HMoiré signal (up to

2.2V peak) is present on pin 3.

If HMoiré/HLock is not selected, pin 3 can be used

as a 0....2.5V DAC.

3 VERTICAL PART

3.1 Function

When the synchronization pulse is not present, an

internal current source sets the free-running fre-

quency. For an external capacitor COSC = 150nF,

the typical free running frequency is 100Hz.

The typical free running frequency can be calculat-

ed by:

fo(Hz) = 1.5 . 10-5 .

A negative or positive TTL level pulse applied on

Pin 2 (VSYNC) as well as a TTL composite sync

on Pin 1 can synchronize the ramp in the range

[fmin, fmax] (See Figure 16 on page 30). This fre-

quency range depends on the external capacitor

connected on Pin 22. A 150nF (

± 5%) capacitor is

recommended for 50Hz to 120Hz applications.

If a synchronization pulse is applied, the internal

oscillator is synchronized immediately but with

wrong amplitude. An internal correction then ad-

justs it in less than half a second. The top value of

the ramp (Pin 22) is sampled on the AGC capaci-

tor (Pin 20) at each clock pulse and a transcon-

ductance amplifier modifies the charge current of

the capacitor so as to adjust the amplitude to the

right value.

The Read Status register provides the vertical

Lock-Unlock and the vertical sync polarity informa-

tion.

We recommend to use an AGC capacitor with low

leakage current. A value lower than 100nA is man-

datory.

A good stability of the internal closed loop is

reached with a 470nF

± 5% capacitor value on Pin

20 (VAGC).

3.2 I2C Control Adjustments

S and C correction shapes can then be added to

this ramp. These frequency-independent S and C

corrections are generated internally. Their ampli-

tudes are adjustable by their respective I

2C regis-

ters. They can also be inhibited by their select bits.

Finally, the amplitude of this S and C corrected

ramp can be adjusted by the vertical ramp ampli-

tude control register.

The adjusted ramp is available on Pin 23 (VOUT)to

drive an external power stage.

The gain of this stage can be adjusted (

± 25%) de-

pending on its register value.

The mean value of this ramp is driven by its own

I2C register (vertical position). Its value is

VPOS = 7/16 . VREF-V ± 400mV.

Usually VOUT is sent through a resistive divider to

the inverting input of the booster. Since VPOS de-

rives from VREF-V, the bias voltage sent to the non-

inverting input of the booster should also derive

from VREF-V to optimize the accuracy (see Appli-

cation Diagram).

3.3 Vertical Moiré

By using the vertical Moiré, VPOS can be modulat-

ed from frame to frame. This function is intended

to cancel the fringes which appear when the line to

line interval is very close to the CRT vertical pitch.

The amplitude of the modulation is controlled by

switched-off via the control bit D8.

COSC

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