HD74HC299 datasheet(2/9 Pages) RENESAS

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HD74HC299

Rev.2.00 Jan 31, 2006 page 2 of 8

Function Table

Inputs

Function

Select

Output

Control

Serial

Inputs/Outputs

Outputs

Mode

Clear

1†

2†

Clock

A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA’

QH’

Clear

QA0

QB0

QC0

QD0

QE0

QF0

QG0

QH0

QA0

QH0

Hold

QA0

QB0

QC0

QD0

QE0

QF0

QG0

QH0

QA0

QH0

QAn

QBn

QCn

QDn

QEn

QFn

QGn

Shift

Right

QAn

QBn

QCn

QDn

QEn

QFn

QGn

QBn

QCn

QDn

QEn

QFn

QGn

QHn

QBn

Shift

Left

QBn

QCn

QDn

QEn

QFn

QGn

QHn

QBn

Load

Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flip-

flop outputs are isolated from the input/output terminals.

2. QA0 to QH0; the level of QA through QH, respectively, before the indicated steady-state input conditions were

established.

3. QAn to QHn; the level of QA through QH, respectively, before the most-recent

transition of the clock.

4. † ; When one or both output controls are high the eight input/output terminals are disabled to the high-

impedance state, however, sequential operation or clearing of the register is not affected.

5. When clear is low, outputs of QA’ and QH’ are low, in spite of other inputs.

Pin Arrangement

G/QC

E/QE

C/QC

A/QA

Clear

GND

VCC

H/QH

F/QF

D/QD

B/QB

Clock

Output

controls

Shift left

Shift right

(Top view)

H/QH

D/QD

B/QB

F/QF

G/QG

E/QE

A/QA

C/QC

Clear

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