M64894FP/GP

Rev.2.00 Jun 14, 2006 page 3 of 12

Pin Arrangement

1

16

8

7

6

5

4

3

2

fin

BS1

BS2

BS3

BS4

GND

Xin

(Top view)

M64894FP/GP

Outline: PRSP0016DA-A (16P2S-A) [FP]

PRSP0016JA-A (16P2Z-A) [GP]

Vin

Vtu

ADC

SCL

SDA

ADS

10

11

12

13

14

15

9

Pin Description

Pin No.

Symbol

Pin name

Function

1

fin

Prescaler input

Input for the VCO frequency.

2

GND

GND

Ground to 0 V.

3

Power supply voltage 1

Power supply voltage terminal. 5.0 V

± 0.5 V

4

Power supply voltage 2

5

6

7

8

BS4

BS3

BS2

BS1

Band switching outputs

PNP open collector method is used.

When the band switching data is “H”, the output is ON.

When it is “L”, the output is OFF.

9

Vin

Filter input

(Charge pump output)

This is the output terminal for the LPF input and charge pump

output. When the phase of the programmable divider output (f

“source” current state becomes active.

If it is behind, the “sink” current becomes active.

If the phases are the same, the high impedance state becomes

active.

10

Vtu

Tuning output

This supplies the tuning voltage.

11

Power supply voltage 3

Power supply voltage for tuning voltage 28 to 35 V

12

ADC/ftest

AD converter input/

Test port

A/D conversion of the input voltage.

In control byte data input, the programmable freq. Divider output

and reference freq. output is selected by the test mode.

13

SCL

Clock input

Data is read into the shift register when the clock signal falls.

14

SDA

Data input

Input for band SW and programmable freq. divider set up.

In lead mode, it outputs lock detector output and power down flag

and a state of 5 level A/D converter.

15

ADS

Address switching input

Chip address sets it up with the input condition of terminal.

16

Xin

This is connected to the

crystal oscillator

4.0 MHz crystal oscillator is connected.