HD74AC175

Rev.2.00, Jul.16.2004, page 2 of 7

Logic Symbol

CP

MR

Pin Names

D

Data Inputs

CP

Clock Pulse Input

MR

Master Reset Input

Q

True Outputs

Q

Complement Outputs

Functional Description

The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and

Q outputs. The Clock

and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High

clock (CP) transition, causing individual Q and

Q outputs to follow. A Low input on the Master Reset (MR) will force

all Q outputs Low and

Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general

logic applications where a common Master Reset and Clock are acceptable.

Truth Table

Inputs

Outputs

@ t

MR

MR

MR = H

@ t

n+1

Dn

Qn

Qn

LL

H

HH

L

H :

High Voltage Level

L

:

Low Voltage Level

t

n

:

Bit Time before Clock Pulse

t

n + 1

: Bit Time after Clock Pulse