HD74HC95

Rev.2.00, Oct 06, 2005 page 2 of 6

Function Table

Inputs

Clocks

Parallel

Outputs

Mode Control

2 (L)

1 (R)

Serial

A

B

C

D

H

H

X

X

X

X

X

X

H

X

X

a

b

c

d

a

b

c

d

H

X

X

d

d

L

L

H

X

X

X

X

X

L

X

H

X

X

X

X

H

L

X

L

X

X

X

X

L

L

L

X

X

X

X

X

L

L

X

X

X

X

X

L

H

X

X

X

X

X

H

L

X

X

X

X

X

H

H

X

X

X

X

X

Notes: 1. H : High level, L : Low level, X : Irrelevant

2. a to d : The level of steady-state input at inputs A, B, C or D respectively

established.

) transition of the clock.

Pin Arrangement

1

A

B

C

D

Mode

CK1

CK2

Outputs

(Top View)

2

3

4

5

6

7

Inputs

A

B

C

D

Mode

Control

Serial

Input

Serial

Input

GND

Vcc

Clock1

R-Shift

Clock2

L-Shift

(Load)

14

13

12

11

10

9

8